Assessment of gait normality using a depth camera and mirrors

This paper presents an initial work on assessment of gait normality in which the human body motion is represented by a sequence of enhanced depth maps. The input data is provided by a system consisting of a Time-of-Flight (ToF) depth camera and two mirrors. This approach proposes two feature types to describe characteristics of localized points of interest and the level of posture symmetry. These two features are processed on a sequence of enhanced depth maps with the support of a sliding window to provide two corresponding scores. The gait assessment is finally performed based on a weighted combination of these two scores. The evaluation is performed by experimenting on 6 simulated abnormal gaits.Comment: 2018 IEEE EMBS International Conference on Biomedical & Health Informatics (BHI

ResCap: Residual Capsules Network for Medical Image Segmentation

Convolutional neural networks (CNNs) have shown remarkable results for a wide range of task in computer vision. However, CNNs has the limitation of poor translation invariance and lack of information about pose; thus, it requires a lot of data. Capsule networks, however, have the ability to preserve information about the pose. In this paper, we present a capsule-based network for medical image segmentation. We adopt the contracting path of the U-Net architecture. The network achieves the same accuracy as U-Net but is much smaller (0.16% number of parameters compared with U-Net)

A FLEXIBLE HIGH-BANDWIDTH LOW-LATENCY MULTI-PORT MEMORY CONTROLLER

Multi-port memory controllers (MPMCs) have become increasingly important in many modern applications due to the tremendous growth in bandwidth requirement. Many approaches so far have focused on improving either the memory access latency or the bandwidth utilization for specific applications. Moreover, the application systems are likely to require certain adjustments to connect with an MPMC, since the MPMC interface is limited to a single-clock and single-data-width domain. In this paper, we propose efficient techniques to improve the flexibility, latency, and bandwidth of an MPMC. Firstly, MPMC interfaces employ a pair of dual-clock dualport FIFOs at each port, so any multi-clock multi-data-width application system can connect to an MPMC without requiring extra resources. Secondly, memory access latency is significantly reduced because parallel FIFOs temporarily keep the data transfer between the application system and memory. Lastly, a proposed arbitration scheme, namely window-based first-come-first-serve, considerably enhances the bandwidth utilization. Depending on the applications, MPMC can be properly configured by updating several internal configuration registers. The experimental results in an Altera Cyclone V FPGA prove that MPMC is fully operational at 150 MHz and supports up to 32 concurrent connections at various clocks and data widths. More significantly, achieved bandwidth utilization is approximately 93.2% of the theoretical bandwidth, and the access latency is minimized as compared to previous designs